Semiconductor memories are formed with memory cells that store bits of data. Various terms such as word and byte are utilized to describe the data stored in certain groups of memory cells. When information is being read out of a semiconductor memory, all the bits that form such a group are normally read simultaneously out of the cells containing those bits. Similarly, if a semiconductor memory is a rewritable memory in that data can be written into each memory cell multiple times, all the bits that form a bit group such as a word or a byte are normally written simultaneously into the memory.
Referring to the drawings, FIG. 1 illustrates the basic architecture for a conventional rewritable semiconductor memory in which all the bits that form a word, byte, or other such bit group are written simultaneously. The memory in FIG. 1 is a flash EPROM of the type generally described in U.S. Pat. No. 6,355,524. Data is stored in a multiplicity of memory cells 20 arranged in rows and columns. Each memory cell 20 is an n-channel split-gate floating-gate field-effect transistor (“FET”) having source S, drain D, floating gate FG, overlying control gate CG, and select gate SG.
Each memory cell 20 is conventionally defined to be in a low logic, or “0”, state when the threshold voltage of the cell's floating-gate FET is sufficiently high that the FET is turned off when a nominal control voltage is applied between control gate CG and source S and a nominal access voltage is simultaneously applied between select gate SG and source S. The logic “0” state is achieved by introducing electrons onto floating gate FG to raise the threshold voltage in a programming operation. Each cell 20 is then conventionally defined to be in a high logic, or “1”, state when the threshold voltage is sufficiently low that application of a nominal control voltage between control gate CG and source S accompanied by simultaneous application of a nominal access voltage between select gate SG and source S causes the FET to turn on. The logic “1” state is achieved by removing electrons from floating gate FG to lower the threshold voltage in an erase operation. Cells 20 that store the bits of a word or byte are situated in a row of cells 20.
Memory cells 20 are addressed through row decoder 22 and column decoder 24. The EPROM of FIG. 1 further includes write buffer 26, sense amplifiers 28, read buffer 30, and input/output circuitry/pins 32 through which the EPROM interacts with the outside world. Row decoder 22 accesses the rows of cells 22 through word lines 34 connected to select gates SG. In addition, decoder 22 is connected to sources S through source lines 36, to control gates CG through control lines 38, and to the cell channel regions through body lines 40. Column decoder 24 accesses the columns of cells 20 through bit lines 42 connected to drains D. A particular group of cells 20 in a row is selected for a read or write operation by utilizing decoder 22 to select the row and utilizing decoder 24 to select the columns having those cells 20.
The EPROM of FIG. 1 receives a pair of supply voltages between which the memory operates during read operations. A write operation is performed by first erasing all of memory cells 20 to logic “1”. A programming operation is then performed on selected cells 20 to write logic “0” simultaneously into those cells 20 by providing their control gates CG and either sources S or drains D with programming voltages considerably greater than the higher of EPROM's two supply voltages for introducing electrons onto their floating gates FG to raise their threshold voltages to the “0” level.
The programming voltages are supplied from internal high-voltage generation circuitry (not separately shown in FIG. 1) and are transmitted along control lines 38 and either source lines 36 or bit lines 42 to memory cells 20. However, voltage losses occur along the circuitry, including lines 38 and either lines 36 or lines 42, that connect the high-voltage generation circuitry to cells 20. Since all the bits in a bit group such as a word or byte are written simultaneously into the EPROM of FIG. 1 and since the number of cells 20 programmed to logic “0” varies from zero to all of the bits in the bit group, the voltage losses commonly vary with the number of cells 20 being programmed to “0”.
In some instances, the variance of the voltage losses with the number of memory cells being programmed to logic “0” may cause the programming voltages to be too high or too low to achieve proper programming. If a programming voltage is too high, the threshold voltages of certain memory cells 20 may be raised too much. This “overprogramming” can lead to incomplete erasure during subsequent operation. Also some of cells 20 may undergo damage due to resultant source-to-body pn junction breakdown or/and gate dielectric breakdown.
If a programming voltage is too low, certain of memory cells 20 may not have their voltages raised sufficiently to reach logic “0”. As a result of this “underprogramming”, those cells 20 may be incorrectly determined to contain logic “1” during read operations. It is desirable to be able to write information into a memory such as EPROM in such a way that the accuracy of the write operation is largely independent of the logic states of the bits being simultaneously written into the memory.